RTL Design Practice Guide - I Combinational Logic - Full Adder

 

1.2 Full Adder:

1.2.1 Description:

A full adder is a fundamental building block of digital circuits that perform addition of three binary digits – two inputs (a and b) and a carry input (cin) – and produces a sum output (sum) and a carry output (carry). From a design perspective, a full adder can be implemented using various logic gates such as AND, OR, XOR, and NOT gates.

The design of a full adder involves combining two half adders with an additional OR gate to handle the carry input. The first half adder takes the two input bits (a and b) and produces a partial sum and a partial carry. The second half adder takes the partial sum and the carry input (cin) and produces the final sum output (sum) and a second partial carry. The final carry output (carry) is generated by combining the two partial carry outputs (output from first and second half adders) using an OR gate.

Full adders are commonly used in many digital systems, such as arithmetic logic units (ALUs), microprocessors, and memory circuits. Efficient and optimized full adder designs are crucial for the overall performance and power consumption of these systems.

1.2.2 Description:

Figure 1.3 shows the block diagram of a full adder


Figure 1.3 - Full adder block diagram

1.2.3 RTL Schematic:

RTL – Register Transfer Level schematic in VLSI – Very Large Scale Integration is a graphical representation of a digital circuit at the register level. It shows how data is transferred from one register to another and how it is processed between them. RTL schematic is used to describe the functionality of the circuit, its data flow, and its timing constraints. It is an important intermediate step in the VLSI design process, used to verify the correctness of the circuit before it is implemented at the gate level. The RTL schematic is typically created using a hardware description language (HDL) such as Verilog or VHDL, and it can be simulation using various tools to ensure that it meets the design requirements. Once the RTL schematic has been verified, it can be synthesized into a gate-level netlist, which can be used to generate the physical layout of the circuit.

Figure 1.4, shows the RTL schematic of a full adder and generated using Verilog hardware description language.


Figure 1.4 - Full adder RTL schematic with half adder blocked

Figure 1.5, shows the RTL schematic of half adder expansion present in a full adder circuit.


Figure 1.5 - Full adder RTL schematic with half adder unblocked

Figure 1.6, shows the gate level representation of a full adder, generated using Verilog hardware description language

 


                                          Figure 1.6 - Full adder gate level RTL schematic

 

1.2.4 Hardware Description Language:

The Verilog and VHDL (VHSIC – Very High Speed Integrated Circuit Hardware Description Language) for a full adder can be constructed using a combination of simpler logic circuits, such as a half adder. A half adder is a combinational circuit that takes two inputs ‘a’ and ‘b’, and produces two outputs ‘sum’ and ‘carry’. The ‘sum’ output is the XOR of ‘a’ and ‘b’, while the ‘carry’ output is the AND of ‘a’ and ‘b’.

1.2.4.1 Verilog: 1-bit full adder using two half adder module

The following Verilog code illustrates the implementation of a full adder using two half adders and an OR gate:

 

// Full adder Top Module

module full_add (a,b,cin, sum,cout);

  input a,b,cin;     // inputs

  output sum, cout;     // output

  wire x,y,z;

  // half adder module instantiation //

  half_add h1 (.a(a), .b(b), .s(x), .c(y));    // half adder module 1

  half_add h2 (.a(x), .b(cin), .s(sum), .c(z)); // half adder module 2

  or o1 (cout, y, z);   // OR gate generates final carry

endmodule

// Half adder module

module half_add(a,b,s,c);

  input a,b;

  output s,c;

  xor x1(s,a,b);  // sum output

  and a1(c,a,b);  // carry output

endmodule

 

1.2.4.2 VHDL: 1-bit full adder using half adders

The following VHDL code illustrates the implementation of a full adder using logic gates such as XOR, AND and OR gates:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is

   port (

     a : in STD_LOGIC;

     b : in STD_LOGIC;

     cin : in STD_LOGIC;

     s : out STD_LOGIC;

     cout : out STD_LOGIC

  

   );

   end full_adder;

   architecture gate_level of full_adder is

   begin

      s <= a xor b xor cin;

      cout <= (a and b) or (cin or a) or (cin and b);

   end gate_level;

 

1.2.5 FPGA Implementation:

FPGA implementation is the process of designing and programming an FPGA device to perform a specific set of functions. Generally, the process involves several steps, including design entry, synthesis, place and route, timing analysis, and bitstream generation.

Below is the synthesised implementation of a full adder and its resource consumption:

                                         Reference Device: xcau15b-ffvb676-2-e

                                         Resource:  LUT – 1

                                                           FF    -- 0

                                                           BRAM – 0

                                                           URAM  -- 0

                                                           DSP   -- 0

                                                           IO  -- 5

                                                           GT – 0

                                                           BUFG – 0

                                                           MMCM – 0

                                                           PLL – 0

                                                           PCIe  -- 0

FPGA Resources for 1-bit full adder

1.2.6 Questions to ask Design Perspective:

Ø  What is the required input range of the full adder?

Ø  What is the output range of the full adder?

Ø  What is the required operating frequency of the full adder?

Ø  How much power can be consumed by the full adder?

Ø  What are the critical path delays in the full adder?

Ø  How many stages of logic gates are required to implement the full adder?

Ø  Can the full adder be implemented using standard cells or does it require custom logic gates?

Ø  What is the area of the full and how does it affect the overall design/

Ø  Are there any other design requirements or constraints for the full adder?

Ø  How will the full adder be tested and verified to ensure correct functionality and performance?


1.2.7 Problem Statements for RTL design practice:

v Implement a full adder using NAND gates only.

v Design a full adder using NOR gates only.

v Implement a full adder design using XOR and AND gates only.

v Design a full adder using only transmission gates.

v Implement a full adder using pass-transistor logic.

v Design a full adder using only two-level logic gates.

v Implement a full adder using a PLA (Programmable Logic Array)

v Design a full adder with minimal gate count and optimal delay.

v Implement a full adder using only combinational logic, without any feedback.

v Design a full adder with minimal power consumption.


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