RTL Design Practice Guide - I : Combinational Logic - Half Adder

 1.1 Half Adder

1.1.1       Description

1.1.2       Block Diagram

1.1.3       RTL Schematic

1.1.4       Hardware Description Language

1.1.5       FPGA Implementation

1.1.6       Questions to ask design perspective

1.1.7       Problem Statements to Design Engineers

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1.1.1 Description:

A half adder is a fundamental digital circuit that performs addition of two binary digits and produces two outputs: a sum bit and a carry bit.

A half adder can be implemented using logic gates such as AND gates and XOR gates. The two inputs to the half adder are the two bits to be added, and the two outputs are the sum bit and the carry bit.

The sum bit is obtained by performing an XOR operation on the two input bits, while the carry bit is obtained by performing an AND operation on the two input bits. The carry bit is used as an input to the next stage of the addition process.

Half adders are used in larger digital circuits such as full adders and arithmetic logic units (ALUs) to perform more complex operations. They are also used in error detection and correction circuits and in various types of digital communication systems.

Figure 1.1 shows the block diagram of a half adder


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1.1.2 RTL Schematic:

RLT Schematic is a type of digital circuit design representation that focuses on the flow of the flow of data between registers in the circuit. It is commonly used in VLSI (Very Large Scale Integration) design to create high-level abstraction of a digital circuit and to aid in the design, simulation, and verification process.

The below RTL schematic Figure 1.2, represents the half adder and it is been created using Verilog Hardware Description Language.



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1.1.3 Hardware Description Language

A Hardware Description Language is a programming language used to describe the behaviour and structure of digital circuits and systems. HDLs are used in digital design, verification, and simulation, and are an essential tool for VLSI (Very Large-Scale Integration) design.

HDLs are similar to software programming languages, but they specialized for describing the hardware elements and interconnections of a digital system. They allow designers to create a high-level abstraction of the system, and to simulation and verify its behaviour before it is physically implemented.

The two most commonly used HDLs are Verilog and VHDL. Verilog was developed in the 1980s by a team at Gateway Design Automation, while VHDL (VHSIC Hardware Description Language) was developed in the 1980s by the U.S. Department of Defence as part of a larger initiative to improve the design and manufacturing of high-performance integrated circuits.

HDLs are used for a variety of digital design tasks, including RTL (Register Transfer Level) design, verification, synthesis, and simulation. They are also used in the development of digital signal processing (DSP) circuits, embedded systems, and other digital applications.

The below are the half adder implementation using Verilog and VHDL hardware description languages.

1.1.3.1 Verilog:

///////////////////////////// half adder using Verilog begin ///////////////////

module ha(a,b,sum,carry);

  input a;    

  input b;  

  output sum;  

  output carry;

  assign carry = a&b;    // carry output AND of input a and b

  assign sum   = a^b;    // sum output XOR of input a and b

endmodule

///////////////////////////// half adder using Verilog end ///////////////////////

------------------------ half adder using VHDL begin ------------------

1.1.3.2 VHDL:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

entity half_adder is

   port (

     a,b: in bit;

     sum, carry : out bit

   );

   architecture data of half_adder is

   begin

     sum <= a xor b;   -- sum output

     carry <= a and b; -- carry output

   end

----------------------- half adder using VHDL end ---------------------

1.1.4 FPGA Implementation:

FPGA implementation is the process of implementing the digital circuits on the FPGA device to perform a specific digital circuit.

Typically, FPGA implementation involves several steps, including design, synthesis, placement and routing, and programming.

The below results are taken from Xilinx Vivado Synthesis design of the half adder.

                                         Reference Device: xcau15b-ffvb676-2-e

                                         Resource:  LUT – 1

                                                           FF    -- 0

                                                           BRAM -- 0

                                                           URAM -- 0

                                                           DSP   -- 0

                                                           IO -- 4

                                                           GT -- 0

                                                           BUFG -- 0

                                                           MMCM -- 0

                                                           PLL -- 0

                                                           PCIe – 0

FPGA Resource utilization

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1.1.5 Questions to ask design perspective:

  • Ø  What is a half adder, and what is its function?
  • Ø  What are the inputs and outputs of a half adder?
  • Ø  How can half adder be implemented using logic gates, and what are the advantages and disadvantages of each implementation method?
  • Ø  What is the propagation delay of a half adder, and how can it be minimized?
  • Ø  What is the power consumption of a half adder, and how can it be reduced?
  • Ø  How can the layout of a half adder be optimized to reduce area and improve performance?
  • Ø  What is signal integrity, and how can it be ensured in a half adder design?
  • Ø  How can noise immunity be ensured in a half adder design?
  • Ø  What are the timing constraints for a half adder, and how can they be met?
  • Ø  What is the design for testability considerations for a half adder, and how can they be addressed?


1.1.6 Problem Statements to the Design Engineers:

  • v Design a half adder using only NAND gates
  • v Design a half adder using only NOR gates
  • v Design a half adder using minimum number of transistors.
  • v Explore alternative implementations of the half adder design, such as using carry lookahead adders or ripple carry adders, and evaluate their advantage and disadvantages.


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